The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). FinFETs have been used in a variety of applications, for example, to implement logic devices/circuits and to provide static random-access memory (SRAM) devices, among others. Generally, logic devices are focused on performance (e.g., high Ion/Ioff ratio, low parasitic capacitance, etc.), while SRAM devices may focus on optimizing cell size and improving cell operation voltage, among other requirements. However, optimization of both logic and SRAM performance and/or design requirements has been challenging. As merely one example, reduction of a FinFET fin critical dimension (CD) may improve logic device Ion/Ioff performance but may also degrade SRAM latch-up performance. Thus, existing techniques have not proved entirely satisfactory in all respects.